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FEATURES 10-Bit, 100 MSPS ADC Low Power: 450 mW at 100 MSPS On-Chip Track/Hold 280 MHz Analog Bandwidth SINAD = 54 dB @ 41 MHz On-Chip Reference 1 V p-p Analog Input Range Single +5 V Supply Operation +5 V/+3.3 V Outputs APPLICATIONS Digital Communications Signal Intelligence Digital Oscilloscopes Spectrum Analyzers Medical Imaging Sonar HDTV GENERAL DESCRIPTION
AD9071
AIN AIN T/H
10-Bit, 100 MSPS A/D Converter AD9071
FUNCTIONAL BLOCK DIAGRAM
VREF IN VREF OUT
VCC - 2.5V VDD ADC 10 ENCODE LOGIC OR ADC
D0-D9
SUM AMP
DAC
ENCODE
TIMING
VCC
GND
The AD9071 is a monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and TTL/CMOS digital interfaces. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. The ADC requires only a single 5 V supply and an encode clock for full performance operation. The digital outputs are TTL compatible. Separate output power supply pins support
interfacing with 3.3 V or 5 V logic. An out-of-range output (OR) is available that indicates a conversion result is outside the operating range. The output data are held at saturation levels during an out-of-range condition. The input amplifier supports differential or single-ended interfaces. An internal reference is included. Fabricated on an advanced BiCMOS process, the AD9071 is available in a plastic SOIC package specified over the industrial temperature range (-40C to +85C).
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD9071-SPECIFICATIONS otherwise noted)
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity1 Integral Nonlinearity1 No Missing Codes1 Gain Error2 Gain Tempco2 ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)3 Output Propagation Delay (tPD)3 Output Rise Time (tR) Output Fall Time (tF) DIGITAL INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY VCC Supply Current (VCC = 5 V)4 VDD Supply Current (VDD = 3.3 V)4 Power Dissipation4 Power Supply Sensitivity5 +25C Full +25C Full +25C +25C Full Full I VI I VI I I VI V Temp
(VCC = +5 V, VDD = +3.3 V, Differential Analog Input, ENCODE = 100 MSPS unless
Test Level
Min
AD9071BR Typ 10 0.8 1.0 0.8 1.25 Guaranteed 1 2 150
Max
Units Bits
+1.5/-1.0 +1.75/-1.0 1.5 1.75 4 8
LSB LSB LSB LSB % FS % FS ppm/C
Full Full +25C Full Full +25C +25C Full +25C Full Full Full Full +25C +25C +25C +25C Full Full Full Full Full Full Full Full +25C Full Full
V V I VI VI V I VI V VI V VI IV IV IV V V VI VI V V VI VI VI VI V VI VI
15
512 -2.5 0.2 4 18 5 20 35 3 55 90 65 115 280 VCC - 2.5 130 VCC - 2.4
mV p-p V mV mV k pF A A MHz V ppm/C MSPS MSPS ns ns ns ps, rms ns ns ns ns V V A A pF V V
VCC - 2.6
100 4.5 4.5 1.1 3.0 4.0 5.0 1.4 1.0 40 13 13
2.0
7.0
2.0 0.8 10 -500 3 VDD - 0.5 0.05 Offset Binary
Full Full Full +25C
VI VI VI I
85 7.5 450 0.002
115 14 620 0.010
mA mA mW V/V
-2-
REV. B
AD9071
Parameter DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 41 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 41 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 41 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 41 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 41 MHz Two-Tone Intermodulation (IMD) fIN = 10.3 MHz fIN = 41 MHz
6
Temp +25C +25C
Test Level V V
Min
AD9071BR Typ 4 5
Max
Units ns ns
+25C Full +25C Full
I V I V
54 53
56 55 55 54
dB dB dB dB
+25C Full +25C Full +25C +25C +25C +25C +25C +25C +25C +25C
I V I V I I I I I I V V
54 52
56 55 54 53 9.2 8.8 75 66 75 65 70 60
dB dB dB dB Bits Bits dBc dBc dBc dBc dBc dBc
8.8 8.5 63 60 65 57
NOTES 1 Differential and integral nonlinearity based on F S = 80 MSPS. 2 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 3 tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 5 pF. 4 Power dissipation is measured under the following conditions: F S @ 100 MSPS, analog input is -1 dBFS at 10.3 MHz. 5 A change in input offset voltage with respect to a change in V CC. 6 SNR/harmonics based on an analog input voltage of -1.0 dBFS referenced to a 1.024 V full-scale input range. Typical thermal impedance for the R style (SOIC) 28-lead package: JC = 23C/W, CA = 48C/W, JA = 71C/W. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Operating Temperature . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
EXPLANATION OF TEST LEVELS Test Level
I.
100% production tested.
II. 100% production tested at +25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9071 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD9071
ORDERING GUIDE
Model AD9071BR AD9071/PCB
Temperature Range -40C to +85C +25C
Package Description 28-Lead Wide Body (SOIC) Evaluation Board
Package Option R-28
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 7, 12, 21, 23 2, 8, 11 3 4 5, 6 9 10 13 14 15-19, 24-28 20, 22
Name GND VCC VREF OUT VREF IN DNC AIN AIN ENCODE OR D9-D0 VDD
Function Ground. Analog Power Supply. Nominally 5.0 V. (Tie together to prevent a possible latch-up condition.) Internal Reference Output (VCC - 2.5 V typical); Bypass with 0.1 F to VCC. Reference Input for ADC (VCC - 2.5 V typical). Do Not Connect. Analog Input - Complementary. Analog Input - True. Encode clock for ADC. (ADC Samples on Rising Edge of ENCODE.) Out-of-Range Output. Goes HIGH when the converted sample is more positive than 3FFH or more negative than 000H (offset binary coding). Digital outputs of ADC. D9 is the MSB. Data is offset binary. Digital Output Power Supply. User selectable range from 3 V to 5 V.
PIN CONFIGURATION
Table I. Output Coding
GND 1 VCC 2 VREF OUT VREF IN DNC DNC GND 3 4 5 6 7
28 D0 27 D1 26 D2 25 D3 24 D4
Code 1023 1023 1022 * * * 513 512 511 * * * 1 0 0
AIN-AIN 0.512 V 0.511 V 0.510 V * * * 0.001 V 0.000 V -0.001 V * * * -0.511 V -0.512 V -0.513 V
Offset Binary 11 1111 1111 11 1111 1111 11 1111 1110 * * * 10 0000 0001 10 0000 0000 01 1111 1111 * * * 00 0000 0001 00 0000 0000 00 0000 0000
OR 1 0 0 * * * 0 0 0 * * * 0 0 1
AD9071BR 23 GND
TOP VIEW 22 VDD (Not to Scale) 21 GND 20 VDD 19 D5 18 D6 17 D7 16 D8 15 D9 (MSB)
VCC 8 AIN 9 AIN 10 VCC 11 GND 12 ENCODE 13 OR 14
DNC = DO NOT CONNECT
-4-
REV. B
AD9071
SAMPLE N-1 AIN SAMPLE N SAMPLE N+3 SAMPLE N+4
tA tEH
ENCODE
SAMPLE N+1
SAMPLE N+2
tEL
1/f s
tPD
D9-D0 DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N
tV
DATA N+1
Figure 1. Timing Diagram
VCC
VDD
AIN
AIN
D9-0, OR
Figure 2. Equivalent Analog Input Circuit
Figure 5. Equivalent Digital Output Circuit
VCC
VCC
VREF IN
VREF OUT
Figure 3. Equivalent Reference Input Circuit
Figure 6. Equivalent Reference Output Circuit
VCC
ENCODE
Figure 4. Equivalent Encode Input Circuit
REV. B
-5-
AD9071-Typical Performance Characteristics
0 -10 -20 -30 -40
dB
dB
0 FUNDAMENTAL = -1.0dBFS SNR = 56.75dB SINAD = 56.56dB 2ND HARMONIC = -71.88dB 3RD HARMONIC = -77.28dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 MHz 50 0 MHz 50 F1 = 41.1MHz F2 = 42.1MHz F1 = F2 = -7.0dBFS
-50 -60 -70 -80 -90 -100
Figure 7. Spectrum: FS = 100 MSPS, fIN = 10.3 MHz
Figure 10. Two-Tone Intermodulation Distortion
0 -10 -20 -30 -40
dB
60 FUNDAMENTAL = -1.0dBFS SNR = 55.23dB SINAD = 54.35dB 2ND HARMONIC = -68.28dB 3RD HARMONIC = -62.83dB 58 56 54 52 dB 50 48 46 44 42 40 0 MHz 50 10 20 40 60 80 fIN - MHz 100 120 140 SINAD SNR
-50 -60 -70 -80 -90 -100
Figure 8. Spectrum: FS = 100 MSPS, fIN = 41 MHz
Figure 11. SINAD/SNR vs. f IN: FS = 100 MSPS
0 -10 -20 -30 -40 F1 = 9.63MHz F2 = 10.63MHz F1 = F2 = -7.0dBFS
58 57 56 SNR 55 54 SINAD
dB
dB
-50 -60 -70 -80 -90 -100 0 MHz 50
53 52 51 50 49 48 10 20 40 60 80 F S - MSPS 100 120 140
Figure 9. Two-Tone Intermodulation Distortion
Figure 12. SINAD/SNR vs. FS: fIN = 10.3 MHz
-6-
REV. B
AD9071
60
60 58
SNR
SNR 56 SINAD 54 52
55
SINAD
dB
50
dB
-15 5 TC 25 55 85
50 48 46
45
44 42
40 -40
40 2.5
3.5
4.5 5.5 ENCODE PULSEWIDTH - ns
6.5
7.5
Figure 13. Differential SNR vs. TC: fIN = 10.3 MHz
Figure 15. SNR vs. Clock Pulsewidth (tEH): fIN = 10.3 MHz
60 58 56 54 52 SINAD SNR
0
-1 -2 -3
-3dB ROLLOFF POINT
dB
50 48 46 44
dB
-4 -5 -6 -7 85
42 40 -40 -15 5 TC 25 55 15 60 105 150 195 240 fIN - MHz 285 330 375 420
Figure 14. Single-Ended SNR vs. TC: fIN = 10.3 MHz
Figure 16. Frequency Response
90 80 70 60
DIFFERENTIAL INPUT
SINGLE-ENDED
dBc
50 40 30 20 10 0 10
20 fIN - MHz
30
40
Figure 17. Second Harmonic Performance: SingleEnded vs. Differential Input
REV. B
-7-
AD9071
APPLICATION NOTES
THEORY OF OPERATION
The AD9071 employs a two-step subranging architecture with digital error correction. The sampling and conversion process is initiated by a rising edge at the ENCODE input. The analog input signal is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit, which captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The coarse quantizer (ADC) produces a 5-bit estimate of the input value. Its digital output is reconverted to analog form by the reconstruction DAC and subtracted from the input signal in the SUM AMP. The second stage quantizer generates a 6-bit representation of the difference signal. The eleven bits are presented to the ENCODE LOGIC, which corrects for range overlap errors and produces an accurate 10-bit result. Data are strobed to the output on the rising edge of the ENCODE input, with the data from sample N appearing on the output following ENCODE rising edge N+3.
USING THE AD9071 ENCODE Input
comparators detect when the analog input signal is out of this range, and set the OR output signal HIGH. The digital outputs are locked at plus or minus full scale (3FFH or 200H) for voltages that are out of range, but between 1 V and 5 V. Input voltages outside of this range may result in invalid codes at the ADC's output.
VREF (+2.5V) 100 0.1 F AIN 50 0.1 F 25 100
AD9071
AIN
Figure 19. Single-Ended Analog Input Configuration
When the analog input signal returns to the nominal range, the out-of-range comparators return the ADC to its active mode and the device recovers in the overvoltage recovery time.
Voltage Reference
Any high-speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9071, and the user is advised to give commensurate thought to the clock source. The lowest jitter clock source is a crystal oscillator producing a pure sine wave. The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
A stable and accurate 2.5 V voltage reference (VCC - 2.5 V) is built into the AD9071 (VREF OUT). In normal operation, the internal reference is used by strapping Pins 3 and 4 of the AD9071 together. The internal reference can provide 100 A of extra drive current that may be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9071, which cannot be obtained by using the internal reference. For these applications, an external 2.5 V reference can be connected to VREF IN, which requires 5 A of drive current (see Figure 20).
+5V
The digital outputs are CMOS compatible for lower power consumption. 200 series resistors are recommended between the AD9071 and the receiving logic to reduce transients and improve SNR.
Analog Input
AD780
+5V 1F GND TRIM +VIN VOUT 1M
0.1 F
AD9071
VREF IN
25k
The analog input has been optimized for differential signal input.
VREF (+2.5V) T1A T1 - 1T 50 0.1 F 100 0.1 F AIN 100
O/P SELECT NC NC = NO CONNECT
Figure 20. Using the AD780 Voltage Reference
AD9071
AIN
The input range can be adjusted by varying the reference voltage applied to the AD9071. No appreciable degradation in performance occurs when the reference is adjusted 4%. The full-scale range of the ADC tracks reference voltage changes linearly.
Timing
Figure 18. Differential Analog Input Configuration
If driven single-endedly, the AIN should be connected to a clean reference and bypassed to ground. For best dynamic performance, impedances at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9071 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +1.988 V to +3.012 V (1.024 V p-p centered at +2.5 V). Out-of-range
The performance of the AD9071 is insensitive to the duty cycle of the clock over a wide range of operating conditions (see Figure 15). The AD9071 provides latched data outputs, with three pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figure 1). The length of the output data lines, and loads placed on them, should be minimized to reduce transients within the AD9071; these transients can detract from the converter's dynamic performance.
-8-
REV. B
AD9071
The minimum guaranteed conversion rate of the AD9071 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may degrade. The AD9070 will operate in bursts, but the user must flush the internal pipeline each time the clock restarts. Valid data will be produced on the fourth rising edge of the ENCODE signal after the clock is restarted.
EVALUATION BOARD
resistor on Data Ready (R33), normally 0 ohms, is provided to support various user output impedance configurations. The AD9760 DAC supports viewing reconstructed A/D data at J4.
Voltage Reference
The AD9071 evaluation board is a convenient and easy way to evaluate the performance of the AD9071 in the SOIC package. The board consists of an internal voltage reference or an optional external reference, two 74LCX574 latches for capturing data from the A/D converter, and an AD9760 DAC for viewing reconstructed A/D data. The AD9071 output logic can be driven at 5 V and 3.3 V levels. The latches are set up at 3.3 V but are 5 V tolerant. Test points are provided at Encode, DB9, DB0, Data Ready, and Data Clock. All are clearly labeled.
Analog Input
The AD9071 can be operated using its internal voltage reference (connect E2 to E3) or an optional external reference (connect E1 to E2). The board is shipped utilizing the internal voltage reference.
Layout
The AD9071 is not layout sensitive if some important guidelines are met. The evaluation board layout provides an example where these guidelines have been followed to optimize performance. * Provide a good ground plane connecting the analog and digital sections. * Excellent bypassing is essential. Chip capacitors with 0.1 F values and 0803 dimensions are placed flush against the pins. Placing any of the capacitors on the bottom of the board can degrade performance. These techniques reduce the amount of parasitic inductance that can impact the bypassing ability of the caps. * Separate power planes and supplies for the analog and digital sections are recommended. The AD9071 evaluation board is provided as a design example for customers of Analog Devices. ADI makes no warranties express, statutory, or implied regarding merchantability or fitness for a particular purpose.
The evaluation board can be driven single-ended or differentially. Differential input requires using a 1:1 transformer. For single-ended operation (J2), Jumper S5 is connected to S8 and S6 is connected to S7. For differential input operation (J3), S5 is connected to S3 and S4 is connected to S6. The board is shipped in the differential configuration.
Encode
The AD9071 encode inputs are driven single-ended into J1 and are at TTL logic levels.
Data Out
The data delivered out of the AD9071 is in offset binary format at TTL levels. The Data Ready signal can be inverted by opening the S1 and S2 connections. An optional series termination
Figure 21. Printed Circuit Board Top Side Silkscreen
Figure 22. Printed Circuit Board Bottom Side Silkscreen
REV. B
-9-
AD9071
Figure 23. Printed Circuit Board Top Side Copper
Figure 25. Printed Circuit Board "Split" Power Layer
Figure 24. Printed Circuit Board Ground Layer
Figure 26. Printed Circuit Board Bottom Side Copper
-10-
REV. B
REV. B
U1 74LCX574 1 OUT EN D0 DB0 DB1 DB2 DB2 R24 100 DB3 DB3 DB4 DB4 R22 100 DB5 R21 100 DB6 19 18 DB6 17 16 15 14 13 12 11 DB7 DB8 DB9 OR Q7 OR DB9 R30 100 DB8 R28 100 DB5 DB7 R29 100 R20 100 DATABIT 5 DATABIT 4 R23 100 DATABIT 3 DATABIT 2 R25 100 DB1 DATABIT 1 GND D1 D2 D3 D4 D5 D6 D7 CLOCK GND : 10 +VD : 20 U2 74LCX574 1 OUT EN D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 D1 D2 D3 D4 D5 D6 D7 CLOCK GND : 10 +VD : 20 TP5 R34 150 6 TP4 +VD J5 GND R35 150 +VD 2 3 4 5 6 TP2 R3 200 9 8 7 11 Q7 12 Q6 13 Q5 14 Q4 15 Q3 16 Q2 17 Q1 18 Q0 19 R26 100 C37DPPF DB0 2 3 4 5 6 R12 200 7 8 9 28 R13 200 R14 200 R15 200 R16 200 R17 200 14 R18 200 R27 100 DATABIT 0 E3
1
R9 200 VREF INT E2
1
TP3 VCC R10 200 R11 200
E1
1
VREF EXT S8 3 VREF OUT VREF IN DNC DNC 4 R1 S5 100 ANALOG IN 6 5 S10 GND 9 AIN AIN 10 S6 ANALOG IN C22 0.1 F R32 25 13 ENCODE OR R19 100
VREF C13 0.1 F
C7 0.1 F
SMB A IN J2 2, 3, 4, 5 - GND
R5 50
C5 0.1 F S3
SMB A IN DIF T1 J3 3 4 R4 2, 3, 4, 50 2 5 - GND
S9
U3 AD9071
6
1
S4
DATABIT 6
T1 - 1T S7
C4 0.1 F
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 27 26 25 24 19 18 17 16 15 DATABIT 7
GND DATABIT 8
SMB 3 ENCODE TP1
ENCODE IN
U5 74LCX86 VCC : 2, 8, 11 VDD : 20, 22 GND : 1, 7 12, 21, 23
J1 2, 3, 4, 5 - GND 11 DATA CLK
R6 50
1 2
DATABIT 9
OVERRANGE R33 0 DATA READY R36 150 R37 150
Figure 27. Printed Circuit Board Schematic
-11-
8 DATA READY VCC C17 0.1 F C6 0.1 F C18 10 F VDD 10 9 8 7 6 5 4 3 2 1 C21 10 F C11 0.1 F C12 0.1 F 28 +VD C15 0.1 F C3 0.1 F C2 0.1 F +VD C14 0.1 F CLK DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9
S1
12 13
S2
9 10
R31 4.99k
4
+VD
5
+ VD : 14 GND : 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 P2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
TB1
1
DATA READY
GND
2
3
VCC
C1 0.1 F
4
5
VDD
+VD
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 22 IOUTA DAC OUT
6
VREF EXT
TB6
C20 10 F
AD9760
IOUTB DVDD AVDD COMP2 COMP1 FSADJ REFIO REFLO SLEEP 19 17 16 18 27 23 24 15 C9 0.1 F R2 2k C10 0.1 F 21 S13 S11 S12 +VD R7 50
SNS J4 2, 3, 4, 5, - GND
C19 10 F
C17 0.1 F
C8 0.1 F
DATABIT 0 DATABIT 1 DATABIT 2 DATABIT 3 DATABIT 4 DATABIT 5 DATABIT 6 DATABIT 7 DATABIT 8 DATABIT 9 OVERRANGE R8 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
AD9071
AD9071
Table II. Printed Circuit Board Bill of Materials
Item # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Quantity 18 4 3 4 1 1 13 1 11 5 1 1 1 4 13 1 1 5 2 1 1 1
Reference C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C22 C18, C19, C20, C21 E1, E2, E3 J1, J2, J3, J4 J5 P2 R1, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30 R2 R3, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18 R4, R5, R6, R7, R8 R31 R32 R33 R34, R35, R36, R37 S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13 T1 TB1 TP1, TP2, TP3, TP4, TP5 U1, U2 U3 U4 U5
Description Ceramic Chip Capacitor, 0603, 0.1 F Tantalum Chip Capacitor, 10 F Jumpers SMB-P Connector 20-Pin Male Header 37-Pin Connector (Amp 747462-4) Surface Mount Resistor, 1206, 100 Surface Mount Resistor, 1206, 2000 Surface Mount Resistor, 1206, 200 Surface Mount Resistor, 1206, 50 Surface Mount Resistor, 1206, 5000 Surface Mount Resistor, 1206, 25 Surface Mount Resistor, 1206, 0 Surface Mount Resistor, 1206, 150 Jumpers Surface Mount Transformer Mini-Circuit T1-T1, 1:1 Ratio 6-Pin Wieland Connector (P/N # 25,602, 2653.0; 25.530 3625.0) Test Points 74LCX574 Octal Latch AD9071BR, 10-Bit, 100 MSPS, ADC AD9760AR, 10-Bit, 125 MSPS, DAC 74LCX86, XOR
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide Body SOIC (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
0.2992 (7.60) 0.2914 (7.40)
1 14
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) SEATING 0.0138 (0.35) PLANE
0.0125 (0.32) 0.0091 (0.23)
8 0
0.0500 (1.27) 0.0157 (0.40)
-12-
REV. B
PRINTED IN U.S.A.
C3331b-0-5/99

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